DSP ENGINeeR – Satellite Comms

The Opportunity

XDLinx Labs is looking for a DSP Engineer with 4–5 years of hands-on experience developing and implementing digital signal processing algorithms for satellite communication systems. You will design, simulate, and deploy the signal processing chains that sit at the heart of our next-generation satellite payloads — from waveform generation and channel coding through to synchronisation, equalisation, and demodulation — across DVB and CCSDS standards — on both FPGA and software-defined radio platforms.

This is an opportunity to work across the full DSP development lifecycle: from algorithm conception in MATLAB/Python, through fixed-point modelling and bit-true simulation, to real-time implementation on Xilinx/Intel FPGAs and embedded processors. You will collaborate closely with RF, systems, and test engineers to ensure your algorithms translate seamlessly from simulation to hardware in a space-grade environment.

What We Can Offer You

  • Investment in innovation: dedicated R&D time to explore novel waveform designs, advanced coding schemes, and AI-assisted signal processing for future satellite programmes.
  • Hands-on access to state-of-the-art FPGA development boards, SDR platforms, channel emulators, and signal analysis equipment from day one.
  • Structured technical career path with mentoring from senior DSP and systems engineers, and support to attend leading industry events (IEEE MILCOM, DVB World, IET Comms).
  • Continuous professional development through training, sponsored certifications, and opportunities to contribute to internal research publications.
  • Inclusive network groups (Enable, Equalise) and a collaborative team culture where your ideas directly shape the products we build.

What You Will Do

You will be responsible for the design and implementation of DSP algorithms and signal processing chains for satellite communication payloads. Working within an agile engineering team, your responsibilities will span the following areas:

Waveform & Modem Design

  • Design and simulate digital communication waveforms for satellite links, including DVB-S2/S2X, DVB-RCS2, and proprietary waveforms, covering modulation (BPSK, QPSK, 8PSK, 16/32APSK), pulse shaping, and spectral containment.
  • Implement CCSDS-compliant telemetry and telecommand processing chains: CCSDS TM/TC synchronisation marker insertion and detection (CCSDS 131.0), Reed–Solomon and LDPC outer coding (CCSDS 131.0-B, 131.1-O), randomisation, Virtual Channel multiplexing, and Space Data Link Protocol (SDLP) framing per CCSDS 132.0 and 133.0.
  • Design and implement CCSDS Proximity-1 and Space Packet Protocol (SPP, CCSDS 133.0) data handling layers; develop frame synchroniser and bit-sync acquisition algorithms for CCSDS-formatted downlink streams with configurable ASM patterns and frame lengths.
  • Develop and optimise forward error correction (FEC) schemes including LDPC, turbo codes, Reed–Solomon, and BCH codes; implement encoder and decoder algorithms in fixed-point arithmetic for FPGA deployment, with specific attention to the CCSDS-standardised rate-1/2 and rate-7/8 LDPC and turbo FEC profiles.
  • Design frame synchronisation, timing recovery, frequency offset estimation, and carrier phase recovery algorithms for robust demodulator operation across varying SNR and Doppler conditions typical of LEO, MEO, and GEO satellite links.
  • Model and simulate the complete link including noise, non-linear amplifier effects (AM/AM, AM/PM), phase noise, and multipath; validate BER/FER performance against theoretical bounds in MATLAB or Python.
  • Implement adaptive equalisation algorithms (LMS, RLS, MMSE) to compensate for channel distortion, group delay variation, and inter-symbol interference in satellite transponder chains.

FPGA Implementation

  • Translate floating-point DSP algorithms into optimised fixed-point FPGA designs using VHDL or Verilog; perform wordlength analysis, quantisation noise modelling, and overflow/saturation analysis to achieve target performance with minimum resource utilisation.
  • Implement real-time DSP pipelines on Xilinx (Zynq, Ultrascale+, Versal) and/or Intel (Arria, Stratix) FPGAs, including AXI4-stream and AXI4-lite bus interfaces for integration with SoC processing systems.
  • Use Xilinx Vivado HLS or Intel oneAPI to accelerate algorithm prototyping; verify HLS-generated RTL against hand-coded reference designs through co-simulation.
  • Develop comprehensive testbenches in VHDL/SystemVerilog and/or ModelSim/QuestaSim; perform timing closure, power analysis, and resource optimisation; write FPGA integration test procedures and sign-off reports.
  • Integrate DSP IP cores with RF front-end interfaces (DAC/ADC, DDC/DUC, NCO, CFR, DPD) and work with hardware engineers to achieve required system dynamic range and linearity.

Software-Defined Radio & Embedded Processing

  • Develop and validate DSP algorithms on SDR platforms (e.g., Ettus USRP, Analog Devices ADRV9009/AD9361, Xilinx RFSoC) using GNU Radio, MATLAB Simulink, or custom C/C++ frameworks.
  • Implement real-time signal processing on embedded processors (ARM Cortex-A/R, DSP cores) using CMSIS-DSP, FFTW, or custom optimised libraries; profile and optimise execution cycles and memory bandwidth.
  • Design and implement software interfaces between DSP subsystems and higher-level communications stack components including CCSDS Space Data Link Protocol layers, Virtual Channel demultiplexing, Space Packet Protocol (SPP) processing, MAC layer, packetisation, and network management functions.
  • Develop Python or C++ test utilities for automated signal generation, capture, and analysis; interface with lab instruments (signal generators, spectrum analysers, oscilloscopes) via VISA/SCPI.

Algorithm Research & Optimisation

  • Research and prototype advanced signal processing techniques for satellite communications including multi-carrier OFDM/OFDMA, spread spectrum, FHSS, and precoding schemes for multi-beam interference mitigation.
  • Develop interference detection and mitigation algorithms; design signal quality monitoring functions (EVM, MER, CNR estimation) for in-orbit telemetry and performance reporting.
  • Investigate and prototype machine learning-based signal processing approaches (e.g., neural network-based equalisation, channel estimation, modulation classification) and assess their viability for embedded deployment on satellite hardware.
  • Conduct literature reviews and produce internal technical notes on emerging waveform standards, coding advances, and PHY layer techniques relevant to satellite communication roadmaps; stay current with CCSDS working group publications, DVB Project updates, and relevant ETSI/ITU-R recommendations.

Verification, Integration & Support

  • Define and execute DSP subsystem verification plans from algorithm-level simulation through hardware-in-the-loop (HIL) testing and end-to-end payload integration; write test procedures, capture results, and document non-conformances.
  • Support RF system integration by characterising DSP performance metrics — EVM, spectral regrowth, CNR, timing jitter, phase noise floor — using vector signal analysers and oscilloscopes; correlate measurements with simulation predictions.
  • Participate in system-level link budget reviews, contributing DSP implementation loss estimates, coding gain values, and modem sensitivity figures to the overall comms chain analysis.
  • Produce clear, auditable technical documentation including algorithm design documents (ADDs), implementation notes, test reports, and interface control documents (ICDs) for internal and customer review.
  • Work closely with systems, RF, mechanical, and test engineers in cross-functional teams; present design progress and results at internal technical reviews and, where appropriate, to external customers or programme stakeholders.

Progression

At XDLinx Labs, this role is the foundation of a clear technical career path in satellite DSP engineering. With demonstrated performance, you will progress toward Senior DSP Engineer within two to three years, taking on algorithmic ownership of complete modem subsystems and leading technical direction for DSP architecture on new satellite programmes. We actively support conference contributions, patent applications, and postgraduate study for engineers who want to deepen their specialism.

Preferred Skills & Experience

You do not need to meet every criterion below. We value a strong algorithmic foundation, curiosity, and genuine hands-on experience above any specific tool set.

DSP Algorithms & Communications Theory

  • Solid grounding in digital communications theory: modulation, demodulation, matched filtering, Nyquist signalling, synchronisation, and FEC coding and decoding.
  • Experience designing and simulating complete satellite modem chains (DVB-S2/S2X, DVB-RCS2, CCSDS, or equivalent proprietary waveforms) including link budget-aware receiver design.
  • Working knowledge of CCSDS standards relevant to satellite communication and data handling: TM/TC synchronisation and channel coding (CCSDS 131.0-B), Space Data Link Protocols (CCSDS 132.0, 133.0), Proximity-1 (CCSDS 211.0), and the CCSDS File Delivery Protocol (CFDP, CCSDS 727.0).
  • Familiarity with channel estimation and equalisation techniques for satellite channels: frequency-selective fading, Doppler shift, non-linear distortion, and phase noise.
  • Knowledge of spread spectrum and anti-jam techniques, OFDM/SC-FDMA waveform design, or multi-beam precoding methods is advantageous.

FPGA Design & HDL

  • Proven FPGA design experience in VHDL or Verilog: RTL coding, simulation, synthesis, place-and-route, and timing closure on Xilinx Vivado or Intel Quartus toolchains.
  • Experience implementing fixed-point DSP cores: FIR/IIR filters, FFT/IFFT, NCO, correlators, FEC encoders/decoders, and AXI-stream interface logic.
  • Familiarity with HLS tools (Vivado HLS, Vitis HLS) and model-based design flows (Simulink HDL Coder, Xilinx System Generator) is an advantage.
  • Understanding of FPGA resource budgeting, pipeline architecture, and timing constraints to meet real-time processing requirements.

Software & Simulation Tools

  • Proficiency in MATLAB and/or Python (NumPy, SciPy, Commpy) for algorithm development, simulation, and post-processing; familiarity with Simulink for system-level modelling.
  • Experience with GNU Radio, Ettus USRP, or Analog Devices SDR platforms for rapid algorithm prototyping and over-the-air testing.
  • Coding ability in C or C++ for embedded DSP implementation and test tooling; familiarity with real-time operating systems (FreeRTOS, VxWorks, or Bare Metal) is a plus.
  • Experience with version control (Git), CI/CD pipelines, and regression testing frameworks for HDL and software codebases.

Lab & Test Skills                                                                                                                

  • Ability to set up and operate RF test equipment: vector signal generators, spectrum analysers, vector signal analysers, oscilloscopes, and BER test sets.
  • Experience capturing and analysing IQ data for modem debug; familiarity with tools such as Keysight 89600 VSA, Rohde & Schwarz WinIQSIM, or equivalent.
  • Ability to write and execute structured test procedures; experience documenting test results and raising non-conformance reports (NCRs).

Personal Qualities

  • Methodical, detail-oriented problem-solver who can move fluidly between high-level algorithm design and low-level bit-true implementation.
  • Strong communicator who can explain DSP concepts clearly to non-specialists, and write concise, well-structured technical documents.
  • Self-motivated and curious: comfortable conducting independent literature reviews and proposing novel approaches to signal processing challenges.
  • Collaborative team player with experience working across multi-disciplinary engineering teams in a structured product development environment.

Qualifications

  • First degree (BEng, MEng, MSc, or PhD) in Electronic Engineering, Communications Engineering, Computer Engineering, Applied Mathematics, or a closely related discipline. Postgraduate qualification or coursework in digital communications or signal processing is strongly preferred.
  • 4–5 years of professional hands-on experience in DSP algorithm development and/or FPGA implementation for communication systems. Internship and postgraduate research experience counts towards this.
  • A demonstrable portfolio of DSP work — simulation results, FPGA designs, or published/internal technical reports — that evidences depth in at least one of: modem design, FEC implementation, or real-time FPGA signal processing.
  • Experience in the satellite, space, or defence sector and familiarity with DVB standards, CCSDS standards (TM/TC, SDLP, SPP, CFDP), ESA ECSS documentation practices, or equivalent is advantageous but not required.

Our Commitment to Diversity & Inclusion

We are unwavering in our commitment to building an inclusive engineering environment. We recognise that diverse perspectives produce better algorithms, better products, and a stronger team. We actively welcome applications from individuals of all backgrounds, regardless of gender, ethnicity, disability, or any other characteristic. If you are passionate about satellite signal processing and your experience speaks to the spirit of this role, we want to hear from you.

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